PCI Express 7.0 presented: This is what the new standard can do

Most consumers are just migrating to PCIe 4.0, but the governing body is a few steps further and is already defining the requirements for PCIe 7.0.

As part of the PCI-SIG Developers Conference 2022, which is currently taking place in the US city of Santa Clara, the standardization body responsible for the PCIe standard (PCIe = PCI Express) announced the first specifications for PCIe 7.0. While PCIe 5.0 is just getting started, the specifications for PCIe 6.0 were finally specified in January of this year. The first devices with PCIe 6.0 came onto the market in April, but it will still be some time before we see SSDs and GPUs that support this standard. PCIe is particularly important in home computers for connecting graphics cards and SSDs. The first details about the successor are already following, but it will only be used for the first time in 2025.

PCI Express 6.0: innovations and availability

The PCIe specifications are defined by the “Peripheral Component Interconnect Special Interest Group” (PCI-SIG for short), an industry consortium based in the USA. Their goal is to publish a new standard every two to three years, the bandwidth of which is doubled compared to its predecessor. You have almost always succeeded in doing this, only the jump from PCIe 2.0 to PCIe 3.0 could not quite meet this requirement. Since then, however, the bandwidth has doubled with each version, including PCIe 7.0 compared to its predecessor PCIe 6.0.

This is what the new standard PCIe 7.0 offers

PCIe 7.0 is expected to deliver 512 GB/s bi-directional throughput over a 16-lane (x16) link, with throughput still impacted by encoding overhead and header efficiency. PCIe 7.0 continues to rely on the 1b/1b flit-mode coding and the PAM4 signaling technology that were introduced with the predecessor and represent a significant improvement over the 28b/130b coding and NRZ signaling. These were used in standards 3.0 through 5.0.

The committee defined the requirements for PCIe 7.0.


The committee defined the requirements for PCIe 7.0.


Due to faster signaling rates, PCIe trace lengths will continue to decrease, resulting in future motherboards requiring more retimers and PCBs made of higher quality materials. This will likely increase the price further. Due to the higher bandwidth per lane, which is bidirectional with PCIe 7.0 at 32 GB/s per lane, “thinner” connections will be possible for some devices.

The specification goals for PCIe 7.0 at a glance:

  • Delivering 128 GT/s raw bitrate and up to 512 GB/s bi-directional over x16 configuration

  • Use of PAM4 signaling (pulse amplitude modulation with 4 levels)

  • Focus on the channel parameters and range

  • Still low latency and high reliability

  • Improving power efficiency

  • Maintaining backwards compatibility with all previous generations of PCIe technology

First end devices not before 2028

Even though the committee has already defined the goals for PCIe 7.0, the final specifications are only planned for 2025. Even if the first devices for data centers and applications such as artificial intelligence and machine learning will come onto the market after a short time, end devices for end customers cannot be expected before 2028.

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